Dear Colleague:
We are pleased to announce the release of a new issue of Journal of Computing Science and Engineering (JCSE), published by the Korean Institute of Information Scientists and Engineers (KIISE). KIISE is the largest organization for computer scientists in Korea with over 4,000 active members.
Journal of Computing Science and Engineering (JCSE) is a peer-reviewed quarterly journal that publishes high-quality papers on all aspects of computing science and engineering. JCSE aims to foster communication between academia and industry within the rapidly evolving field of Computing Science and Engineering. The journal is intended to promote problem-oriented research that fuses academic and industrial expertise. The journal focuses on emerging computer and information technologies including, but not limited to, embedded computing, ubiquitous computing, convergence computing, green computing, smart and intelligent computing, and human computing. JCSE publishes original research contributions, surveys, and experimental studies with scientific advances.
Please take a look at our new issue posted at http://jcse.kiise.org <http://jcse.kiise.org/> . All the papers can be downloaded from the Web page.
The contents of the latest issue of Journal of Computing Science and Engineering (JCSE)
Official Publication of the Korean Institute of Information Scientists and Engineers
Volume 14, Number 3, September 2020
pISSN: 1976-4677
eISSN: 2093-8020
* JCSE web page: http://jcse.kiise.org
* e-submission: http://mc.manuscriptcentral.com/jcse
Editor in Chief: Insup Lee (University of Pennsylvania)
Il-Yeol Song (Drexel University)
Jong C. Park (KAIST)
Taewhan Kim (Seoul National University)
JCSE, vol. 14, no. 3, September 2020
[Paper One]
- Title: Exploring Time-Predictable and High-Performance Last-Level Caches for Hard Real-Time Integrated CPU-GPU Processors
- Authors: Xin Wang and Wei Zhang
- Keyword: GPU; Cache partitioning; Cache locking; Real-time systems; Integrated CPU-GPU
- Abstract
Time predictability is crucial for hard real-time and safety-critical systems. In an integrated CPU-GPU (graphic processing units) architecture, the shared last-level cache (LLC) can cause a large number of interferences between CPU and GPU LLC accesses with diverse patterns and characteristics, which can significantly impact the performance and time predictability of both CPUs and GPUs. In this paper, we explore cache partitioning, locking, and a combination of them to make the LLC time-predictable for integrated CPU-GPUs while achieving high performance. By evaluating these LLC management approaches, we can provide real-time system developers recommendations on the most effective timepredictable LLC designs for heterogeneous CPU-GPU multicore processors.
To obtain a copy of the entire article, click on the link below.
JCSE, vol. 14, no. 3, pp.89-101
<http://jcse.kiise.org/PublishedPaper/year_abstract.asp?idx=359&page_url=Cur
rent_Issues>
[Paper Two]
- Title: GPGPU Functional Units Power Gating for Leakage Energy Reduction
- Authors: Xin Wang and Wei Zhang
- Keyword: GPGPUs; Energy-efficiency; Execution units; Power-gating
- Abstract
The execution units of GPUs (graphics processing units) have been observed to produce many idle cycles that could be a tremendous waste of energy consumption which meanwhile provides a hint to build a more energy-efficient system to operate GPUs if idle cycles can be appropriately taken care of.
However, power-gating without foresight can be dangerous since inaccurate decisions on power-gating will introduce unaffordable overhead on both energy consumption and performance. In this paper, we examine the length of execution units' idle cycles for several representative GPGPU applications and evaluate the distribution of the idleness durations. We then propose the energy-saving strategies with focus on discovering potential execution units' power-gating opportunities. The idle durations are recorded in the runtime for various computing units in streaming multiprocessors (SMs) including integer units and floating units in streaming processors (SPs) and special function units (SFUs). By analyzing the observed idleness, we propose to enhance the energy efficiency through two execution units'
power-gating policies, the immediate power-gating (IPG) and idle detect power-gating (ID-PG). Furthermore, we examine the policies with various parameter settings to offer insights on possible gains and losses of the power-gating techniques. Besides, by noticing that integer units are the most popular computing units for many applications, we introduce the power-aware SP(s) to increase the throughput of integer instructions. It was observed that the power-aware SP can provide performance enhancement as well as the leakage energy reduction for several applications. The experimental results show that both the policies can result in satisfactory leakage energy saving on execution units. The IPG can reduce the execution unit's leakage energy by 84.3% when the break-even time is set to 5 cycles. Even if the break-even time goes up to 20 cycles, the ID-PG can save 67.1% of the total execution units' leakage energy. Moreover, involving power-aware SP(s) can improve the performance by up to 14.4% and 2.7% on average.
To obtain a copy of the entire article, click on the link below.
JCSE, vol. 14, no. 3, pp.102-111
<http://jcse.kiise.org/PublishedPaper/year_abstract.asp?idx=360&page_url=Cur
rent_Issues>
[Paper Three]
- Title: Augmented Museum Experience with Interactive Visualization: Korean Mummy
- Authors: Jihoon Cho, Hyunsoo Kim, Rosaleen Rhee, and Jinah Park
- Keyword: Interactive visualization; Haptic rendering; Volume rendering
- Abstract
We have developed interactive content about Korean mummy to augment the exhibition that is already going on at the Korean Natural History Museum in Korea. This paper introduces the concept of employment of visualization techniques to bring out the intriguing story of a Korean mummy. Haptic rendering and volume rendering are the main algorithms implemented for excavation of a mummy and exploration of the mummy's internal body. Touch screen interface and a haptic device were utilized for intuitive interaction for general public use, especially for children. The virtual contents were formulated based on the information displayed on the wall panels and exhibited at the museum on site. The interactive display fetched more attention to the exhibit and provided a better understanding of the contents. From our survey, it is encouraging to learn that the children who experienced the interactive exhibition showed their interest to revisit the museum.
To obtain a copy of the entire article, click on the link below.
JCSE, vol. 14, no. 3, pp.112-120
<http://jcse.kiise.org/PublishedPaper/year_abstract.asp?idx=361&page_url=Cur
rent_Issues>
[Paper Four]
- Title: Real-Time Scheduling for Periodic Tasks on Uniform Multiprocessors
- Authors: Sang-Gil Lee and Cheol-Hoon Lee
- Keyword: Real-time scheduling; Real-time tasks; Task-splitting
- Abstract
The problem of scheduling a set of periodic tasks on a uniform multiprocessor system is considered in the present study. Each processor in a uniform multiprocessor system is characterized by its speed or computation capacity, i.e., execution of a job on a processor with speed s for t time units completes s x t units of execution. In the commonly-known partitioned scheduling, each task is assigned to a processor and all of its jobs are required to be executed on that processor. However, partitioning of periodic tasks requires solving the bin-packing problem, which is known to be intractable (NPhard in the strong sense). This paper presents a global scheduling algorithm that transforms a given periodic task system into another using a "task-splitting" (as opposed to the "set-splitting"
technique. Each transformed periodic task system is guaranteed to be scheduled successfully on any uniform multiprocessor using a partitioned scheduling algorithm. The earliest deadline first (EDF) algorithm is chosen for scheduling tasks on each processor. It is proven that the proposed algorithm results in the theoretical-maximum utilization bound on any uniform multiprocessor platform if the platform is "reasonably powerful".
Therefore, the proposed algorithm is optimal in the sense of maximizing achievable utilization. Since the task-splitting technique will incur context switches during runtime, we have also considered the ways of reducing the number of context switches, and suggest a method which can significantly reduce the number of context switches in the schedules generated by the proposed algorithm.
To obtain a copy of the entire article, click on the link below.
JCSE, vol. 14, no. 3, pp.121-130
<http://jcse.kiise.org/PublishedPaper/year_abstract.asp?idx=362&page_url=Cur
rent_Issues>
[Call For Papers]
Journal of Computing Science and Engineering (JCSE), published by the Korean Institute of Information Scientists and Engineers (KIISE) is devoted to the timely dissemination of novel results and discussions on all aspects of computing science and engineering, divided into Foundations, Software & Applications, and Systems & Architecture. Papers are solicited in all areas of computing science and engineering. See JCSE home page at http://jcse.kiise.org <http://jcse.kiise.org/> for the subareas.
The journal publishes regularly submitted papers, invited papers, selected best papers from reputable conferences and workshops, and thematic issues that address hot research topics. Potential authors are invited to submit their manuscripts electronically, prepared in PDF files, through <http://mc.manuscriptcentral.com/jcse> http://mc.manuscriptcentral.com/jcse,
where ScholarOne is used for on-line submission and review. Authors are especially encouraged to submit papers of around 10 but not more than 30 double-spaced pages in twelve point type. The corresponding author's full postal and e-mail addresses, telephone and FAX numbers as well as current affiliation information must be given on the manuscript. Further inquiries are welcome at JCSE Editorial Office, <mailto:office@kiise.org> office@kiise.org (phone: +82-2-588-9240; FAX: +82-2-521-1352).